1. Field of the Invention
The present invention relates to a logic circuit using switching devices, in each of which conduction between an input terminal and output terminal is turned ON or OFF according to a potential at a control terminal, as pass transistors to realize desired logic. In particular, this invention is concerned with a logic circuit capable of realizing complex logic while improving operation speed by decreasing the number of stages of pass transistors required to be connected in series. Furthermore, the present invention relates to a logic circuit capable of realizing logic functions, for which many transistors are needed in conventional pass-transistor logic circuits, using a smaller number of transistors, and having characteristics of high operation speed and small power consumption.
2. Description of the Related Art
What is referred to as a "pass-transistor logic circuit" that aims to minimize the number of circuit elements or improve operation speed has been suggested (for example, U.S. Pat. No. 4,541,067). Pass-transistor logic circuits use pass transistors each comprising a switching device. Conduction between an input terminal and output terminal of the switching device is turned ON or OFF according to a potential at a control terminal. Each pass transistor is realized by connecting the switching devices so that whether a logic signal applied to the input terminal is transmitted to the output terminal can be determined with the conducting or nonconducting state of each switching device. In general, a plurality of pass transistors are connected in series and/or parallel to constitute a pass-transistor logic circuit for calculating a desired logical operation. AS for the switching devices, MOS transistors, for example, may be used. In this case, the gate, source, and drain of each MOS transistor correspond to the control, input, and output terminals, respectively.
Using this kind of pass-transistor logic circuit, reportedly, the number of required circuit elements can be decreased and operation speed can be improved.
For example, U.S. Pat. No. 4,559,609 has disclosed that when pass transistors (referred to as transmission gates in the patent) are used to constitute a full adder, the number of transistors can be reduced to a smaller number than when only NOR gates formed with MOS transistors are used.
"Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs" written by K. Yano et al. (IEEE 1994 Custom Integrated Circuits Conference. p. 603-606) has disclosed three kinds of calls Y1 to Y3 to be used for a pass-transistor logic circuit which are shown in FIG. 1. In any of the cells Y1 to Y3, N-channel MOS transistors M1 to M6 are used to constitute a pass-transistor logic circuit. An inverter I is connected to each pass-transistor logic circuit. The cell Y1 a single-stage pass-transistor logic circuit, the cell Y2 is a pass-transistor logic circuit made by combining single-stage and dual-stage pass-transistor logic circuits, and the cell Y3 is a dual-stage pass-transistor logic circuit. The inverter I is composed of N-channel MOS transistors M1 and M2 and P-channel MOS transistors M3 to M5 as shown in FIG. 2.
As for the foregoing pass-transistor logic circuit, various forms have been proposed. An example of a known pass-transistor logic circuit will be described by taking for example a circuit for calculating the AND of input logic signals A and B (A.multidot.B) or the NAND of signals A and B (A.multidot.B). Here, if a logic signal is .alpha., .alpha. denotes a complementary logic signal of the logic signal .alpha., or a logic signal that is active low.
FIG. 3 shows an example of a pass-transistor logic circuit having circuitry referred to as a cascode voltage switch logic (CVSL). N-channel MOS transistors M1 and M2 are connected in series with their source and drain coupled, and also connected to the drain of a P-channel MOS transistor M5. N-channel MOS transistors M3 and M4 are connected in parallel with their drains coupled, and also connected to the drain of a P-channel MOS transistor M6. The sources of the P-channel MOS transistors M5 and M6 are connected to a first power supply means for supplying a power supply potential (VDD). The sources of the N-channel MOS transistors M2, M3, and M4 are connected to a second power supply means for supplying a reference potential. In this example, a ground (GND) potential is supplied as the reference potential. An input logic signal A is input to the N-channel MOS transistor M1 through its gate, while an input logic signal A is input to the N-channel MOS transistor M3 through its gate. An input logic signal B is input to the N-channel MOS transistor M2 through its gate, while an input logic signal B is input to the N-channel MOS transistor M4 through its gate. A result of the AND of the signals A and B (A.multidot.B) is output through the drain of the P-channel MOS transistor M6. A result of the NAND of the signals A and B (A.multidot.B) is output through the drain of the P-channel MOS transistor M5.
FIG. 4 shows an example of a logic circuit having the circuitry referred to as complementary pass transistor logic (CPL). An input logic signal A is input to an N-channel MOS transistor M1 through its source, while an input logic signal A is input to an N-channel MOS transistor M3 through its source. An input logic signal B is input to N-channel MOS transistors M1 and M3 through gates thereof, while an input logic signal B is input to N-channel MOS transistors M2 and M4 through gates thereof. The N-channel MOS transistors M1 and M2 are connected in parallel with their drains coupled, and also connected to the drain of the P-channel MOS transistor M5. The N-channel MOS transistors M3 and M4 are connected in parallel with their drains coupled, and also connected to the drain of the P-channel MOS transistor M6. A result of the AND of the signals A and B (A.multidot.B) is output through the drain to the P-channel MOS transistor M6 via an inverter I1. A result of the NAND of the signals A.multidot.B (A.multidot.B) is output through the drain of the P-channel MOS transistor M5 via an inverter I2.
In the circuit diagrams of FIG. 4 and thereafter, VDD denoting the first power supply means and GND denoting the second power supply means are omitted. In the circuit diagram of FIG. 4 and thereafter, a line terminated with a symbol T shall be connected to the first power supply means, and a line terminated with a symbol of an inverted triangle shall be connected to the second power supply means.
FIG. 5 shows an example of a swing restored pass transistor logic (SRPL). FIG. 6 shows an example of a differential split-level CMOS logic. FIG. 7 shows an example of a double pass-transistor logic (DPL). FIG. 8 shows an example of a differential cascode voltage switch with the pass gate (DCVSPG). In any of FIGS. 5 to 8, input logic signals A and B and A and B are converted into output logic signals A.multidot.B and A.multidot.B.
A full adder configured using only CMOS logic gates shown in FIG. 9 and a full adder using a CPL logic circuit shown in FIG. 10 are compared with each other in terms of the number of transistors required, operation speed, power consumption, and the like.
To begin, as shown in FIG. 9, inverters I1 to I3 are used to produce inverted input logic signals A to C that are complementary to input logic signals A to C. In FIG. 10, inverted input logic signals are produced in the same manner, though details are not shown.
A signal representing a result of addition, Sum, is produced by N-channel MOS transistors M1 to M10, P-channel MOS transistors M16 to M25, and an inverter I4. A carry, Cout, is produced by N-channel MOS transistors M11 to M15 P-channel MOS transistors M26 to M30, and an inverter I5.
By contrast, in the full adder of a CPL shown in FIG. 10, signals representing results of addition, Sum and Sum, are produced by N-channel MOS transistors M1 to M4, and M17 to M20, and inverters I1 and I2. Carries Cout and Cout are produced by N-channel MOS transistors M5 to M16, and inverters I3 and I4.
The number of transistors, speed, power consumption, product of a power and delay time (PD), and product of an energy and delay time (ED) are listed in Table 1 relative to the full adder using only CMOS logic gates shown in FIG. 9, the full adder of a CPL shown in FIG. 10, and the full adders using various kinds of pass-transistor logic circuits of the DPL, DCVSPG, and SRPL types ("A High Speed, Low Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications" written by A. Parameswar et al. Proceedings of IEEE 1994 Custom Integrated Circuit Conference. p. 278-281). The design rule is 0.4 micrometers. Note that the PD and ED are indices used to assess performance and that smaller PD and ED values indicate better performance.
TABLE 1 ______________________________________ 0.4 .mu.m device (full adder) Power Con- sumption Number of Speed (mw/100 PD ED Transistors (ns) MHz) (Relative value) ______________________________________ Ordinary 40 0.82 0.52 1.00 1.00 CMOS CPL 28 0.44 0.42 0.43 0.23 DPL 48 0.63 0.58 0.86 0.66 DCVSPG 24 0.53 0.30 0.37 0.24 SRPL 28 0.48 0.19 0.21 0.13 ______________________________________
As apparent from Table 1, compared to a full adder configured using CMOS gates alone, when a full adder is configured using a CPL, DCVSPG, or SRPL pass-transistor logic circuit, the number of required transistors is smaller, the speed is higher, and the power consumption is less. As for the PD and ED indices, a full adder using any of the pass-transistor logic circuits is superior to the full adder using CMOS logic gates alone.
However, for realizing various logical operation other than a full adder, generally, it has not been made clear whether a pass-transistor logic circuit is more advantageous than a logic circuit using CMOS logic gates alone (hereinafter referred to simply as a CMOS logic circuit).
Moreover, in known pass-transistor logic circuits, a plurality of pass transistors are connected in series and/or parallel to express desired logical operations. For confining the decay of a signal to be transmitted to a permissible range, the number of pass transistors to be connected in series or parallel is limited. When the number of stages increases, the delay time required until an input logic signal is output varies greatly depending on an input position. This poses the problem that it becomes hard to verify the operating timing of a logic circuit. For avoiding this kind of problem, preferably, the number of stages or trees should be decreased. However, a single-stage pass-transistor logic circuit can handle only three variables (input logic signals) at maximum and can be used merely to realize a logic circuit capable of expressing two product terms each containing two variables. A dual-stage pass-transistor logic circuit can deal with up to seven variables and can express up to four product terms each containing three variables. On the other hand, a triple-stage pass-transistor logic circuit can deal with up to 15 variables and express eight product terms each containing four variables. However, intense restrictions are imposed on such product terms containing a large number of variables. It is hard to efficiently express various logical operations with them.
Moreover, in a pass-transistor logic circuit, desired logical operations are expressed by connecting a plurality of pass transistors in series or parallel. The larger the number of pass transistors to be connected, the larger the series resistance or parallel capacitance becomes. The increase in resistance or capacitance leads to a decrease in rise or fall speed of the output signal. When the rise or fall speed decreases, the operation speed decreases. In addition, power consumption by the logic circuit in the succeeding stage creases, and a noise margin decreases.
Furthermore, it is a problem that the logical amplitude (difference in potential between HIGH and LOW states) of an output logic signal decreases. The decrease in the logical amplitude decreases the noise margin of the logic circuit in the succeeding stage. For example, when an N-channel MOS transistor is used to form a pass transistor, if a signal of a VDD potential is applied to the source thereof acting as an input terminal, the potential of a signal to be applied to the drains acting as an output terminal is lowered substantially to a potential VDD-Vtn-.alpha.. Here, Vtn denotes a threshold voltage of the N-channel MOS transistor when a substrate potential is equal to a source potential, and a denotes a change in the threshold voltage caused by a back gate effect. By contrast, when a P-channel MOS transistor is used to form a pass transistor, if a signal of a GND potential is applied to the source thereof, the potential of a signal transmitted to the drain is raised substantially to a potential .vertline.Vtp+.beta..vertline.. Here, Vtp denotes a threshold voltage of the P-channel MOS transistor when a substrate potential is equal to a source potential, and .beta. denotes a change in threshold voltage caused by the back gate effect. This kind of decrease in logical amplitude is inevitable when normally-OFF type switching devices (such as enhancement mode MOS transistors) are used to form pass transistors.
In an effort to solve the problem of a decrease in logical amplitude, it has been proposed to pull up an output of a pass transistor using P-channel MOS transistors, pull it down using N-channel MOS transistors, or pull it up or down using a small inverter. For example, in the pass-transistor logic cells shown in FIG. 1, a pull-up circuit composed of the P-channel MOS transistors M3 and M4 and the N-channel MOS transistor M1 is included in the inverter I shown in FIG. 2. However, when the pull-up or pull-down is thus carried out, the problem arises that load capacitance relative to a logic circuit in a preceding stage becomes larger, signal delay is extended, and power consumption and chip area increase.
As shown in FIG. 11 taken from "CMOS3 Cell Library" by Heinbuch p. 138, it has been proposed to combine an N-channel MOS transistor and P-channel MOS transistor to form each pass transistor. This combination is often called a pass gate or transmission gate. In this circuit, a P-channel MOS transistor drives the potential at an output terminal to VDD. While, an N-channel MOS transistor drives the potential at the output terminal to GND potential. Signal transmission can therefore be achieved without a decrease in logical amplitude. However, since the driving capacities of the N-channel MOS transistor and P-channel MOS transistor must be retained at a satisfactory level, the gate width of the P-channel MOS transistor is made generally about twice as large as the gate width of the N-channel MOS transistor. The area of a semiconductor chip needed to manufacture a semiconductor integrated circuit made by combining required logic circuits to realize a desired function becomes much larger than that of a semiconductor chip needed to manufacture a semiconductor integrated circuit using N-channel MOS transistors to form pass transistors. In FIG. 11, numerical values written in parentheses after the reference number of each transistor represent gate length and gate width.